AMD has commenced volume production and shipments of its latest Spartan UltraScale+ family of Field-Programmable Gate Arrays (FPGAs), targeting cost-sensitive applications at the network edge. The initial rollout includes the three smallest devices in the series: the SU10P, SU25P, and SU35P, which are now available for order.
These new FPGAs are engineered to deliver a powerful combination of high I/O density, low power consumption, and advanced security features. They are built upon AMD’s established UltraScale+ architecture, ensuring a reliable and high-performance foundation for developers.
A key highlight of the Spartan UltraScale+ family is its integration of state-of-the-art security, including hard IP for post-quantum cryptography with NIST-approved algorithms. This provides robust protection for device configuration and user data through features like a true random number generator (TRNG), a physical unclonable function (PUF), and secure hashing.
“Engineers working on cost-optimized, compact FPGAs require simplicity and a rapid path to market,” stated a representative from AMD. “The Spartan UltraScale+ FPGAs deliver on this by combining a proven architecture with modern connectivity and security, all within a low-risk development path.”
The new devices boast the industry’s highest ratio of I/O to logic, featuring high-density I/O for 3.3V support alongside new high-speed XP5IO. This makes them ideal for a wide range of applications, including industrial, medical, and machine vision. For these higher-performance applications, AMD notes that the Spartan UltraScale+ FPGAs offer a two-speed-grade advantage over competing products.
Additional features new to the AMD Cost-Optimized Portfolio include:
- An integrated memory controller for LPDDR4X/5.
- Support for high-speed differential interfaces like LVDS and MIPI D-PHY.
- Compliant PCIe® Gen4 hard IP for both endpoint and root port applications.
- An octal SPI interface for faster configuration.
Support for the new FPGAs is available in the AMD Vivado Design Suite 2025.1, with the free Standard Edition providing a comprehensive toolset for simulation, verification, and implementation. This, combined with the promise of “push-button timing closure” for less complex designs, aims to streamline the development process and accelerate time to market.
